1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device which includes a dielectric film such as a ferroelectric thin film, and a method of manufacturing the same, and more particularly to a non-volatile semiconductor memory device using a heat-resistant metal and a method of manufacturing the same.
2. Description of Related Art
As a non-volatile semiconductor memory devices there is a ferroelectric semiconductor memory device in which a ferroelectric thin film having a polarization hysteresis is used for a capacitor section. In recent years, the ferroelectric semiconductor memory device is also required to be manufactured with a high density. As a result, the ferroelectric semiconductor memory device has been developed such that a transistor, wiring and a capacitor section are manufactured in a small size and contact holes are manufactured with high aspect ratio.
FIG. 1 is a circuit diagram illustrating a memory capacitor cell of a conventional ferroelectric semiconductor memory device using a ferroelectric thin film. The memory capacitor cell is composed of an NMOSFET as a transfer gate 1 and a ferroelectric capacitor 4. The ferroelectric thin film is provided between a charge storing electrode 2 and a plate electrode 3. The gate electrode of the NMOSFET 1 is connected to a word line 5. One of the diffusion layers of the NMOSFET is connected to a bit line 6 and the other diffusion layer is connected to the charge storing electrode 2 of the ferroelectric capacitor 4. The plate electrode 3 is connected to a plate line.
FIG. 2 is a circuit block diagram illustrating a general ferroelectric random access memory device (to be referred to as an FRAM device hereinafter). In this circuit of a fixed plate line voltage, the plate line voltage controller is not necessary (the plate lines are not shown). In the other circuit of a switched plate line voltage, a voltage controller circuit block is necessary (not shown). The FRAM device is composed of a memory circuit section 7 in which memory capacitor cells are arranged in row and column directions in a matrix manner and a CMOS logic circuit section 8 operable to read or write a data from or in each memory capacitor cell.
As shown in FIG. 1, because the transfer gate 1 of the memory capacitor cell is composed of an NMOSFET, only n.sup.+ regions are formed as the diffusion layers in a portion of a silicon substrate corresponding to the memory circuit section. On the other hand, in the CMOS logic circuit section, the diffusion layers of a PMOSFET are p.sup.+ regions and the diffusion layers of an NMOSFET are n.sup.+ regions. That is, the P.sup.+ diffusion regions and the n.sup.+ diffusion region are mixedly present in a portion of the silicon substrate corresponding to the CMOS logic circuit section.
A first conventional example of such an FRAM device, is reported in "A Half-Micron Ferroelectric Memory Cell Technology with Stacked Capacitor Structure" by Onishi et al. in an international electron device conference (IEDM, Technical Digest, pp. 843-845, 1994). FIGS. 3A to 3D are cross sectional views of the FRAM device proposed by Onishi et al. in the manufacturing process. The method of manufacturing the FRAM proposed by Onishi will be described.
First, as shown in FIG. 3A, two adjacent NMOSFET transfer gates 1 in the memory circuit section 7 and a PMOSFET 9 and an NMOSFET 10 of the CMOS circuit section 8 are formed on a silicon substrate 11. Each MOSFET is separated from each other by element separation oxidation films 35. A first interlayer insulating film 12 is formed on the substrate 11 and the surface of the first interlayer insulating film 12 is flattened in a chemical mechanical polishing (CMP) method. Subsequently, an opening portions (to be referred to as a capacitor contact hole hereinafter) reaching the n.sup.+ diffusion layer of each of the NMOSFET transfer gates 1 through the first interlayer insulating film 12 is formed in the memory circuit section. The n.sup.+ polysilicon film is deposited on the first interlayer insulating film 12 by a CVD method such that the capacitor contact holes are filled with the polysilicon film. Then, the polysilicon film on the first interlayer insulating film 12 is removed in a dry etching back method. As a result, the n.sup.+ capacity plugs 13 are formed in which the capacitor contact holes are filled with the n.sup.+ polysilicon film.
Next, as shown in FIG. 3B, a Pt/TiN/Ti film which functions as the charge storing electrode is formed on the first interlayer insulating film surface by a sputtering method. Then, after a composite alkoxide solution composed of alkoxides of Pb, Ti and Zr is spin-coated on the charge storing electrode film, the substrate is annealed at the temperature of about 600.degree. C. As a result, a PZT film (Pb(Ti,Zr)O.sub.3) having the thickness of about 3000 .ANG. is formed. The PZT film is crystalized by lamp annealing method in which the substrate is heated at the temperature of 660.degree. C. for 30 sec. Subsequently, the Pt/TiN/Ti/PZT film is patterned by an ECR high density plasma etching using a chloric gas. As a result, the structure is obtained in which the PZT film 14 is formed on the charge storing electrode 2 composed of the Pt/TiN/Ti film. Next, a TiO.sub.2 barrier film (not illustrated) is deposited by a sputtering method on the substrate and then a SiO.sub.2 film as the second interlayer insulating film 15 is deposited by a CVD method. A contact hole 16 (to be referred to as a plate electrode hole hereinafter) is formed to reach each of the PZT films 14 through the second interlayer insulating film 15. A Pt film of about 2000 .ANG. is deposited on the substrate by a sputtering method and then the Pt film is patterned by a dry etching using the chloric gas. As a result, the plate electrode 3 composed of the Pt film is formed. In this manner, a capacitor section 4 is formed through the above-mentioned process to have the structure which is composed of the charge storing electrode 2 formed of the Pt/TiN/Ti film on n.sup.+ capacitor plug 13, the Pt plate electrode 3 and the PZT film 14 sandwiched between the charge storing electrode 2 and the plate electrode 3, as shown in FIG. 3B.
Next, as shown in FIG. 3C, a SiO.sub.2 film is deposited as the third interlayer insulating film 17 on the substrate. Then, there is formed an opening portion 18 (to be referred to as a bit contact hole 18 hereinafter) to reach the NMOSFET diffusion layer of the memory circuit section 7 through the laminated film which is composed of the first interlayer insulating film 12, the second interlayer insulating film 15 and the third interlayer insulating film 17. Also, opening portions 19 (to be referred to as CMOS contact holes 19 hereinafter) are formed to reach the diffusion layers and the gate electrode of the CMOS circuit section through the laminated film which is composed of the first interlayer insulating film 12, the second interlayer insulating film 15 and the third interlayer insulating film 17. At the same time, a plate contact hole (not illustrated) which is the opening to the Pt plate electrode 3 through the third interlayer insulating film 17 is formed.
Finally, as shown in FIG. 3D, aluminium is deposited on the substrate by a sputtering method and the deposited film of aluminum is patterned by a dry etching. Thus, a bit line 6 of the memory circuit section 7 and an aluminum wiring pattern 20 of the CMOS logic circuit section 8 are collectively formed.
The first conventional example of the FRAM device formed from a series of processes mentioned above has the following features:
1 the ferroelectric capacitor is formed on n.sup.+ capacitor plug 13, PA1 2 the bit line 6 of the aluminum wiring film is formed on the ferroelectric capacitor 4, and PA1 3 the bit contact hole 18 and the CMOS contact holes 19 to the n.sup.+ diffusion layer and P.sup.+ diffusion layer are partially filled with the aluminum wiring film by the sputtering method. PA1 1 the ferroelectric capacitor 4 is formed on the bit line 6, PA1 2 the n.sup.+ diffusion layers of the NMOSFET transfer gates 1 and the upper capacitor electrode 43 (the charge storing electrode 2) are connected by the local wiring pattern 21, and PA1 3 the opening portions (the local wiring contact hole 61 and the CMOS contact holes 19) penetrating the first to third interlayer insulating films 12, 15 and 17 are partially filled with the aluminum film by the MOCVD method after the ferroelectric capacitor section 4 is formed. PA1 forming on a substrate a CMOS section composed of an N-channel MOS transistor and a P-channel MOS transistor and a memory section composed of at least a transfer gate MOS transistor; PA1 forming a plurality of conductive plugs to penetrate a laminate insulating film to the MOS transistors, the laminate insulating film being composed of a first insulating film and a second insulating film; PA1 forming a capacitor section on the laminate insulating film, the capacitor section being composed of an upper electrode, a dielectric film and a lower electrode; PA1 forming a third insulating film on the laminate insulating film and the capacitor section; and PA1 forming a wiring pattern on the third insulating film to partially penetrate the second insulating film to the plurality of conductive plugs. PA1 forming the first insulating film on the substrate, the CMOS section and the memory section; PA1 forming a bit line wiring pattern on the first insulating film to penetrate the first insulating film to the transfer gate MOS transistor; and PA1 forming the second insulating film on the first insulating film to complete the laminate insulating film. In addition, the method may further include the steps of: PA1 forming the first insulating film on the substrate, the CMOS section and the memory section; PA1 etching the first insulating film to form a trench pattern and to form first contact holes to the MOS transistors, a part of the first contact holes being connected to the trench pattern; PA1 filling the trench pattern and first contact holes with a film composed of conductive heat resistant material; PA1 forming the second insulating film on the first insulating film; PA1 forming second contact holes to penetrate the second insulating films to remaining ones of the first contacts which are not connected to the trench pattern; and PA1 filling the second contact holes with a film composed of conductive heat resistant material to complete the plurality of conductive plugs.
A second conventional example of the FRAM device is proposed by Tanabe et al. in "A Ferroelectric Capacitor over Bit-line (F-COB) Cell for High Density Nonvolatile Ferroelectric Memories" (1995 Symposium on VLSI Technology Digest of Technical Papers, PP. 123-124). FIGS. 4A to 4C are cross sectional views illustrating the manufacturing process of the second conventional example of the FRAM device proposed by Tanabe et al. The method of manufacturing the FRAM will be described.
First, referring to FIG. 4A, a memory circuit section 7 composed of two NMOSFET transfer gates 1 and a CMOS logic circuit section 8 composed of a PMOSFET 9 and an NMOSFET 10 are formed on a silicon substrate 11. The first interlayer insulating film 12 is deposited by a CVD method and the surface of the first interlayer insulating film 12 is flattened by a chemical mechanical polishing (CMP) method. Next, an opening portion (a bit contact hole 18) is formed to reach the n.sup.+ diffusion layer of the NMOSFET 1 through the first interlayer insulating film 12. Subsequently, the tungsten silicide (WSi.sub.x) film is deposited on the substrate 11 by a sputtering method and then patterned by a reactive dry etching. In this manner, a bit line 6 is formed.
Next, as shown in FIG. 4B, the second interlayer insulating film 15 is deposited on the substrate 11 by a CVD method and then flattened by the chemical mechanical polishing (CMP) method. Thereafter, a Pt/Ti film is deposited for the lower electrode of the capacitor section 41 by a sputtering method and further a PZT film 14 is grown by a sol/gel method. The PZT film 14 is subjected to annealing at the temperature of 600.degree. C. in an oxygen gas to be crystalized. Then, the PZT film 14 and the Pt/Ti film 41 are patterned. Next, a Pt film is deposited by a sputtering method and the upper capacitor electrode 43 is formed on PZT film 14 by dry etching the Pt film using a chloric system gas. In the second conventional example of the FRAM device, the lower electrode 41 of Pt/Ti is the plate electrode 3 and the upper electrode 43 is the charge storing electrode 2. After the third interlayer insulating film 17 is formed, opening portions (to be referred to as local wiring contact holes 61 hereinafter) are formed to reach the diffusion layers of the NMOSFET transfer gates 1 of the memory circuit section 7 through the first to third interlayer insulating films 12, 15 and 17, and to reach the upper electrode 43 through the third interlayer insulating film 17. Also, opening portions (to be referred to as CMOS contact holes 19) are formed to reach the n.sup.+ diffusion layer and gate electrode of the NMOSFET 10, and the P.sup.+ diffusion layers of the PMOSFET 9 in the CMOS circuit section 8 through the first to third interlayer insulating films 12, 15 and 17.
Finally, as shown in FIG. 4C, after a TiN/Ti barrier film (not illustrated) is deposited by a sputtering method, a TiN film (not illustrated) and an aluminum film are deposited by an MOCVD method. Subsequently, the Al/TiN/Ti laminate film is patterned by a reactive dry etching. As a result, an aluminium local wiring pattern 21 which connects the diffusion layer of the NMOSFET transfer gates 1 in the memory circuit section and the Pt upper capacitor electrode 43 (the charge storing electrode 2) and an aluminum wiring pattern 20 which connects between CMOS circuits are formed.
The second conventional example of the FRAM device formed through a series of above-mentioned processes has the following features:
The third conventional example of the DRAM device is proposed by Kang et al. in "Highly Manufacturable process Technology for Reliable 256 Mbit and 1 Gbit DRAMs" (1994 IEDM, Technical digest, pp. 635-638, 1994). In the third conventional example of the DRAM device fabrication process, which is applicable to an FRAM device fabrication process, a tungsten film is grown by a CVD method before a capacitor section is formed and the tungsten film is used for a bit line. The method of manufacturing the third conventional example of the DRAM device will be described. FIGS. 5A to 5D are cross sectional views illustrating the manufacturing process of the DRAM device proposed by Kang et al.
First, as shown in FIG. 5A, NMOSFET transfer gates 1 of the memory circuit section 7 and a PMOSFET 9 and an NMOSFET 10 of the CMOS circuit section 8 are formed on a silicon substrate 11. Side wall insulating films are formed on the sides of gate electrodes 22 of the MOSFETs. After an interlayer insulating film is deposited, opening portions are formed to reach the n.sup.+ diffusion layers of the NMOS transfer gates 1 of the memory circuit section. By performing a CVD method and an etching back method, n.sup.+ polysilicon plugs 23 are formed at the opening portions. Further, after a first interlayer insulating film 12 is deposited on the substrate 11 by a CVD method, the surface of the first interlayer insulating film 12 is flattened by a CMP method. Thereafter, an opening portion (bit contact hole) 18 is formed to reach the n.sup.+ polysilicon plug 23 through the first interlayer insulating film 12. Next, a Ti film (not illustrated) is deposited on the substrate 11 by a sputtering method. A lamp annealing is performed to the Ti film to react Ti with polysilicon such that a titanium silicide film is formed on the n.sup.+ contact plug 23 (not illustrated). Next, after a TiN barrier film (not illustrated) is deposited on the substrate 11 by a reactive sputtering method, a tungsten film 24 is deposited on the TiN film by a CVD method. The laminate film is patterned by a reactive ion etching using a photo-resist pattern as a mask. As a result, a tungsten bit line 24 is obtained. However, at this time, a tungsten contact plug is not formed to reach the CMOS circuit section.
Next, as shown in FIG. 5B, a second interlayer insulating film 15 is deposited on the substrate 11 and opening portions (capacitor contact holes 25) are formed to reach the n.sup.+ polysilicon plugs 23 through the second interlayer insulating film 15. Thereafter, cylindrical charge storing electrodes 25 of the n.sup.+ polysilicon are formed on the capacitor contact plugs 23. Then, a film of Ta.sub.2 O.sub.3 as a high permitivity substance is deposited and etched such that the Ta.sub.2 O.sub.3 26 are formed on the surface of the cylindrical charge storing electrode 25. Next, after a TiN barrier film is deposited by a sputtering method and patterned, an n.sup.+ polysilicon plate electrode 3 is formed by a CVD method. Through a series of processes mentioned above, a capacitor section is formed to have the Ta.sub.2 O.sub.3 film 26 as the capacitive film on the storing electrodes 25.
Next, as shown in FIG. 5C, a third interlayer insulating film 17 is deposited by a CVD method, an opening portion (a plate contact holes 27) is formed to reach the n.sup.+ polysilicon plate electrode 3 through the third interlayer insulating film 17. Also, opening portions (CMOS contact holes 19) are formed to reach the diffusion layers of the CMOS circuit section 8 through the first to third interlayer insulating films 12, 15 and 17 and to reach the tungsten bit line film 24 through the second and third interlayer insulating films 15 and 17.
Finally, as shown in FIG. 5D, after a TiN/Ti barrier film (not illustrated) is deposited by a collimator sputtering method, an Al film is deposited on the surface by a high temperature sputtering method and the formed Al film is patterned. In this manner, the CMOS contact holes 19, the plate contact hole 27 and the bit line contact are collectively filled with aluminum. Lastly, a reactive etching is performed to the Al/TiN/Ti film such that an aluminum wiring pattern 20 is formed.
However, there are the following problems in the structure and manufacturing method of the conventional FRAM devices.
First, in the first conventional example of the FRAM device proposed by Onishi et al., the bit line 6 is formed on the ferroelectric capacitor 4. Therefore, the bit contact hole 18 is very deep to reach the transfer gate 1 through the first to third interlayer insulating films 12, 15 and 17. It is difficult for such a deep bit contact hole 18 to be filled with the aluminum film by the sputtering method. It would be possible to expand the diameter of the bit contact hole 18 such that it can be filled with the aluminium film easier. As a result, however, the size of the memory capacitor cell increases in area, so that the high density integration cannot be achieved. Further, because electrostatic coupling is formed between the aluminum film filling the bit contact and the ferroelectric capacitor 4, the capacity of the bit line 6 increases such that the bit line drive ability is decreased.
In the second conventional example of the FRAM device proposed by Tanabe et al., the capacitor on bit-line (COB) structure is used in which the ferroelectric capacitor 4 is formed on the bit line 6 to reduce the bit line capacity. However, for the use of the COB structure, the local wiring contact hole 61 to the NMOS transfer gates 1 and the CMOS contact holes 19 to the diffusion layers of the PMOSFET 9 and the NMOSFET 10 of the CMOS circuit section 8 becomes further deeper by the thickness of the bit line 6 at least. As a result, it becomes further difficult to fill the local wiring contact holes 61 and the CMOS contact holes 19 with the aluminum film only by the sputtering method. Therefore, it is necessarily required to grow the aluminium film by an MOCVD method such that the contacts is filled with the Al film.
By the way, if composite metal oxide such as PZT is exposed to the reducing ambient of hydrogen and so on, oxygen atoms are quitted so that oxygen defects are caused in the crystal. The oxygen defects causes the decrease of a remaining polarization value and the increase of leakage current, resulting in degradation of the ferroelectric characteristic of the capacitor section. In the growth of the Al film by the MOCVD method, a hydrogen gas is generally used as a carrier gas. For this reason, it is not preferred that the Al film is grown by the MOCVD method after the ferroelectric capacitor section is formed. In this manner, because the metal CVD process can not be used after the ferroelectric capacitor section is formed, direct application of the method of manufacturing a DRAM device to the FRAM device process would be limited.
In the third conventional example of the FRAM device proposed by Kang et al., the method of Kang et al. corresponds to the DRAM device manufacturing process and the tungsten bit line 24 is formed using the CVD method before the Ta.sub.2 O.sub.3 film capacitor section is formed. However, it is not tried that when the tungsten bit line is formed, the opening portions (the CMOS contact holes 19) to reach the diffusion layers to the CMOS circuit section 8 are filled with tungsten which is heat-resistant material such that the heat-resistant metal contact plugs are formed at the same time of the formation of the tungsten bit line.
It could be considered that the Kang's method can be applied to the FRAM device manufacturing process by replacing the film of Ta.sub.2 O.sub.3 as a high dielectric material with the ferroelectric film such as the PZT film. However, the opening portions (the CMOS contact holes 19) are very deep to reach the diffusion layers of the CMOS logic circuit section through the first to third interlayer insulating films 12, 15 and 17. In order to deposit the aluminum film using the reflow sputtering method for filling such deep opening portions 19, a high temperature of equal to or higher than 450.degree. C. is required. The ferroelectric film is damaged because of the heat during this sputtering method or the heat stress, resulting in increase of leak current and the decrease of a remaining polarization value. That is, it is impossible to directly apply the method of forming the DRAM device by Kang et al. to the method of forming the FRAM device.
The above mentioned problems relates to the formation of the wiring pattern in the FRAM device. There is remained another problem in the method of forming the ferroelectric capacitor section. In a case that PZT is used as the material of the ferroelectric thin film, the annealing for crystallization of the PZT film after the deposition of the PZT film needs to be performed in the oxygen ambient. Therefore, it is required that the lower capacitor electrode which is provided under the PZT thin film has resistance to oxidation. For this reason, Pt is generally used for the lower capacitor electrode. However, both of PZT and Pt are materials difficult to perform dry etching.
In addition, as shown in FIG. 6A, when the laminate film 29 composed of the PZT film 14 and the Pt lower capacitor electrode film 41 is patterned using a photo-resist pattern 28 as a mask, side wall deposition films 30 mainly composed of the PZT film and the Pt film is deposited on the side walls of the photoresist 28. When the photoresist 28 is removed by an oxygen plasma ashing process, the side wall deposition films 31 like the rabbit's ears are left on the PZT/Pt film pattern, as shown in FIG. 6B. The rabit ear-like side wall deposition films 31 are removed by a mechanical process in which a rotating brush 32 is used. In this case, the PZT film surface 33 is rubbed by the rotating brush 32, so that fine flaws and crystal defects are caused which are one of reasons of degradation of the ferroelectric characteristics of the PZT film.
As described above, the conventional methods of manufacturing the FRAM device is suffering from filling the deep contact holes extending to the diffusion layers with wiring metal without damaging the ferroelectric capacitor section. Accordingly, it is difficult to ensure the reliability of the wiring. Further, in a case where the rabit ear-like side wall deposition films are removed which are formed when the ferroelectric film formed on the lower electrode film of Pt and so on is patterned, a damage is given the surface layer of the ferroelectric film. The characteristic of the FRAM device are degraded even because of these two problems.